The present invention relates to driver interface circuits of the type used to interface between logic signals having a low drive capability and large capacitive loads requiring high speed, high voltage drive signals. In particular, the present invention relates to an improved buffer circuit wherein the level shifted logic input is used to power gate the high current buffer during inactive periods and thereby minimize the power consumption of the buffer during the inactive periods.
A common problem encountered by logic circuit designers in many designs is that of having to drive large capacitive loads but only having low voltage, low drive capability logic signals present. This problem becomes especially acute where it is necessary to drive MNOS type devices which require an especially large voltage swing (i.e. approximately 30 volts) between logic states. While buffers such as the hereinafter described National Semiconductor, Inc. Part No. LH 0033 are available to the circuit designer, these buffers generally consume large amounts of power during inactive periods. This large current consumption however, presents a problem in itself to the designer who is additionally faced with power consumption requirements. Therefore, it is the primary objective of the present invention to minimize the amount of power consumed in such an interface circuit during inactive periods of the logic input signal. This objective is achieved via the novel use of the logic input signal to power gate (i.e. switch-off) the high current buffer.
It is an additional objective of the present invention to minimize the amount of circuitry and logic signals necessary to accommodate the power gating objective.
It is a still further objective of the present invention to provide power gating without affecting the buffer's speed, voltage or other drive characteristics.
These objects are achieved in the present invention via the use of the input logic signal as a power gate input to the voltage follower buffer, thereby switching off the buffer during inactive periods and minimizing the concurrent power consumption.